The present invention relates generally to the field of semiconductor technology, and more particularly to semiconductor manufacture.
Semiconductor device scaling to smaller feature sizes is facing significant challenges. Traditional semiconductor materials and processes for device formation become less effective as physical dimensions shrink down to the nanometer regime. With this reduction in feature size, the thickness of gate dielectrics layers has continually decreased. As gate layers become thinner, a number of issues arise. Time-related voltage breakdowns, hot carrier effects, and diffusion of impurities from the gate electrode to the substrate may occur which can adversely affect the stability of transistors formed with thinner gate dielectric materials. The migration to high-k gate dielectric materials that improve gate current density for a similar effective oxide thickness may be done for improved electrical performing in shrinking devices particularly, in sub-micron regimes.
Negative bias temperature instability (NBTI) is a key reliability issue in metal-oxide semiconductor field-effect devices (MOSFET). NBTI is observed as an increase in the threshold voltage with an associated decrease in drain current and transconductance of semiconductor devices over time. NBTI occurs when a gate electrode is negatively biased at high temperatures, which may result in a drift in the electrical performance of a MOSFET device. NBTI is of particular concern in p-channel devices that operate at high temperatures with negative gate to source voltage. With the introduction of high k dielectrics and the use of metal gates, a similar mechanism, positive bias temperature instability (PBIT) may be observed with n-channel devices when a positive gate to source voltage is applied at high temperatures over time.